In typical pipeline communication system, for example the advanced microcontroller bus architecture high performance bus (AHB) protocol system, there may be resources such as memory or peripheral (referred to as slaves) which are accessible by multiple or single master on system such as CPU and DMA. All the masters in system may not follow the same bus protocol to fetch data or write data to resources.
AHB is well known pipelined protocol and one the important signal on AHB protocol is HREADY. Slave uses HREADY signal to detect or to decide when to process a new access (for example, read or write to/from the memory). Further, the HREADY signal is driven by the slave to indicate status of a current access. When ECC error is detected upon access then slaves have a mechanism in the AHB protocol to respond to the master with an ERROR-RESPONSE. An error response is generated by modulating the HREADY signal and the HREP signal as per the AHB protocol.
In the system where the memory resources are ECC or Parity enabled i.e memory data is protected by ECC or parity then slave need to check for the correctness of the data when the data is read from the memory. Upon a read access from the master, if slave detects an error in the data being read from the memory then slave responds with ERROR-RESPONSE. Due to this, the state of HREADY cannot be determined a cycle before the access is complete as data from the memory is available in the last cycle of the data phase of the access. In the last cycle of the data phase, HREADY should overwritten by the ECC or Parity check logic to force HREADY to either low or high. HREADY will be forced to low if the errors are found. Hence a significant delay is introduced by memory access time and ECC check logic.